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K7D803671B K7D801871B
Document Title
8M DDR SYNCHRONOUS SRAM
256Kx36 & 512Kx18 SRAM
Revision History
Rev No. Rev. 0.0 Rev. 0.1 Rev. 0.2 History -Initial document. -ZQ tolerance changed from 10% to 15% -Stop Clock Standby Current condition changed from VIN=VDD-0.2V or 0.2V fixed to VIN=VIH or VIH -VDDQ Max. changed to 2.0V SA0, SA1 defined for Boundary Scan Order -Deleted -HC16 part(Part Number, Idd, AC Characterisctics) - Absolute Maximum ratings VDDQ changed from 3.13V to 2.825V - LBO input level changed from High/Low to VDDQ/VSS - Stop Clock Standby Current condition changed from K=Low, K=High to K=Low, K=Low - tCHQV/tCLQV changed from 0.1ns to 0.2ns for -33 part from 0.1ns to 0.2ns for -30 part from 0.1ns to 0.25ns for -25part - tCHQX/tCLQX changed from -0.3ns to -0.2ns for -33 part from -0.3ns to -0.2ns for -30 part from -0.4ns to -0.25ns for -25part - tCHQZ/tCLQZ changed from 0.1ns to 0.2ns for -33 part from 0.1ns to 0.2ns for -30 part from 0.1ns to 0.25ns for -25part - tKXCH changed from 1.8ns to 1.7ns for -33 part - tKXCL changed from 1.8ns to 1.7ns for -33 part - Clarification on the features and the timing waveforms regarding the burst controllability. - Recommended DC operating conditions for Clock added. - AC test conditions for VDDQ=1.8V and Single ended clock added. (AC Test Conditions 2) - Package thermal characteristics added. - Add-HC35 part(Part Number, Idd, AC Characteristics) - Absolute Maximum Rating VDDQ changed from 2.825V to 2.4V - VCM-CLK Min changed from 0.6V to 0.68V - Add-HC37 part(Part Number, Idd, AC Characteristics) Draft Data July. 2000 Aug. 2000 Oct. 2000 Remark Advance Advance Advance
Rev. 0.3
Nov. 2000
Advance
Rev. 0.5 Rev. 0.6 Rev. 0.7
Jan. 2001 Feb. 2001 Mar. 2001
Prelimary Prelimary Prelimary
Rev. 1.0
May. 2001
Final
Rev. 2.0 Rev. 3.0
Sep. 2001 Jan. 2002
Final Final
Rev. 4.0
Jan. 2002
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
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January. 2002 Rev 4.0
K7D803671B K7D801871B
FEATURES
* * * * * * * * * * * * * * * * *
256Kx36 & 512Kx18 SRAM
Maximum Frequency 370MHz 357MHz 333MHz 300MHz 250MHz 370MHz 357MHz 333MHz 300MHz 250MHz Access Time 1.7* 1.7* 1.7* 1.9* 2.0* 1.7* 1.7* 1.7* 1.9* 2.0*
Organization Part Number 256Kx36 or 512Kx18 Organizations. Maximum Frequency : 370MHz (Data Rate : 740Mbps) 2.5V VDD/1.5V VDDQ (2.0V max VDDQ). K7D803671B-HC37 HSTL Input and Outputs. K7D803671B-HC35 Single Differential HSTL Clock. 256Kx36 K7D803671B-HC33 Synchronous Pipeline Mode of Operation with Self-Timed Late Write. Free Running Active High and Active Low Echo Clock Output Pin. K7D803671B-HC30 Asynchronous Output Enable. K7D803671B-HC25 Registered Addresses, Burst Control and Data Inputs. Registered Outputs. K7D801871B-HC37 Single and Double Data Rate Burst Read and Write. K7D801871B-HC35 Burst Count Controllable With Max Burst Length of 4 512Kx18 K7D801871B-HC33 Interleved and Linear Burst mode support Bypass Operation Support K7D801871B-HC30 Programmable Impedance Output Drivers. K7D801871B-HC25 JTAG Boundary Scan (subset of IEEE std. 1149.1) 153(9x17) Pin Ball Grid Array Package(14mm x 22mm). NOTE : *Access time equals tKXCH/tKXCL
FUNCTIONAL BLOCK DIAGRAM
SA[0:17]( or SA[0:18]) Address Register CE 18(or 19) 16(or 17) (Burst Address) Burst Counter (Burst Write Address) 18(or 19) 16(or 17) 36(or 18)x2 2 : 1 MUX Write Buffer CE R/W LD Internal Clock Generator G Data Output Strobe Data Output Enable State Machine 36(or 18) DQ CQ,CQ XDIN Strobe_out Output Buffer Echo Clock Output Data In Register (2 stage) 2:1 MUX Memory Array 256Kx36 or (512Kx18)
Dec. Data Out
K,K
Clock Buffer
Data In 36(or18)x2 W/D Array 36(or18)x2
36(or 18)x2 S/A Array
Comparator B1 B3 Advance Co Control SD/DD
Write Address Register (2 stage) CE
B2
Synchronous Select & R/W control
PIN DESCRIPTION
Pin Name K, K SA SA0, SA1 DQ CQ, CQ B1 B2 B3 G LBO Pin Description Differential Clocks Synchronous Address Input Synchronous Burst Address Input (SA0 = LSB) Synchronous Data I/O Differential Output Echo Clocks Load External Address Burst R/W Enable Single/Double Data Selection Asynchronous Output Enable Linear Burst Order Pin Name ZQ TCK TMS TDI TDO VREF VDD VDDQ VSS NC Pin Description Output Driver Impedance Control Input JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output HSTL Input Reference Voltage Power Supply Output Power Supply GND No Connection
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January. 2002 Rev 4.0
K7D803671B K7D801871B
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7D803671B(256Kx36)
1 A B C D E F G H J K L M N P R T U VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS 2 VDDQ DQ VDDQ DQ VDDQ CQ1 VDDQ DQ VDDQ DQ VDDQ CQ1 VDDQ DQ VDDQ DQ VDDQ 3 SA SA SA NC VSS DQ VSS DQ VSS DQ VSS DQ VSS NC VDD SA TMS 4 SA VSS SA VSS VDD VDD VSS VDD VDD VSS LBO VDD VDD VSS SA VSS TDI 5 ZQ B1 G VDD VREF VDD K K VDD B2 B3 VDD VREF VDD SA1 SA0 TCK
256Kx36 & 512Kx18 SRAM
6 SA VSS SA VSS VDD VDD VSS VDD VDD VSS MODE VDD VDD VSS SA VSS TDO
7 SA SA SA SA VSS DQ VSS DQ VSS DQ VSS DQ VSS SA VDD SA NC
8 VDDQ DQ VDDQ DQ VDDQ CQ2 VDDQ DQ VDDQ DQ VDDQ CQ2 VDDQ DQ VDDQ DQ VDDQ
9 VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS
* Mode Pin(6L) is a internally NC.
K7D801871B(512Kx18)
1 A B C D E F G H J K L M N P R T U VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS 2 VDDQ DQ VDDQ NC VDDQ CQ1 VDDQ NC VDDQ DQ VDDQ NC VDDQ DQ VDDQ NC VDDQ 3 SA SA SA NC VSS NC VSS DQ VSS NC VSS DQ VSS SA VDD SA TMS 4 SA VSS SA VSS VDD VDD VSS VDD VDD VSS LBO VDD VDD VSS SA VSS TDI 5 ZQ B1 G VDD VREF VDD K K VDD B2 B3 VDD VREF VDD SA1 SA0 TCK 6 SA VSS SA VSS VDD VDD VSS VDD VDD VSS MODE VDD VDD VSS SA VSS TDO 7 SA SA SA SA VSS DQ VSS NC VSS DQ VSS NC VSS SA VDD SA NC 8 VDDQ NC VDDQ DQ VDDQ NC VDDQ DQ VDDQ NC VDDQ CQ1 VDDQ NC VDDQ DQ VDDQ 9 VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS
* Mode Pin(6L)is a internally NC.
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January. 2002 Rev 4.0
K7D803671B K7D801871B
FUNCTION DESCRIPTION
256Kx36 & 512Kx18 SRAM
The K7D803671B and K7D801871B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 262,144 words by 36 bits for K7D803671B and 524,288 words by 18 bits for K7D801871B, fabricated using Samsung's advanced CMOS technology. Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and falling edge of K clock for a double data rate (DDR) write operations. Data outputs are updated from output registers off the rising edges of K clock for SDR read operations, and off the rising and falling edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access time for all SDR and DDR operations. The chip is operated with a single +2.5V power supply and is compatible with Extended HSTL input and output. The package is 9x17(153) Ball Grid Array balls on a 1.27mm pitch.
Read Operation(Single and Double)
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by burst order off the second rising and falling edge of K clock. Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4. To avoid data contention,at least one NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation only when K clock is in the stop mode. Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and are equal to RQ/5. For example, 250 resistor will give an output impedance of 50. Output driver impedance tolerance is 15% by test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 continuous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
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January. 2002 Rev 4.0
K7D803671B K7D801871B
TRUTH TABLE
K L G X X L L X X X B1 X H L L L L H B2 X L H H L L H B3 X X H L H L X DQ Hi-Z Hi-Z DOUT DOUT DIN DIN B
256Kx36 & 512Kx18 SRAM
Operation Clock Stop No Operation, Pipeline High-Z Load Address, Single Read Load Address, Double Read Load Address, Single Write Load Address, Double Write Increment Address, Continue
NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care". - K & K are complementary.
BURST SEQUENCE TABLE
4 Burst Operation for Interleaved Burst (LBO = VDDQ)
Interleaved Burst A1 First Address
Case 1
A0 A1
Case 2
A0 A1
Case 3
A0 A1
Case 4
A0
Fourth Address
0 0 1 1
0 1 0 1
0 0 1 1
1 0 1 0
1 1 0 0
0 1 0 1
1 1 0 0
1 0 1 0
NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V.
4 Burst Operation for Linear Burst (LBO = VSS)
Linear Burst Mode First Address
Case 1
A1 A0 A1
Case 2
A0 A1
Case 3
A0 A1
Case 4
A0
Fourth Address
0 0 1 1
0 1 0 1
0 1 1 0
1 0 1 0
1 1 0 0
0 1 0 1
1 0 0 1
1 0 1 0
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January. 2002 Rev 4.0
K7D803671B K7D801871B
BUS CYCLE STATE DIAGRAM
256Kx36 & 512Kx18 SRAM
LOAD NEW ADDRESS
,B B2
3
B2 ,B
B1 B2 ,B
3
3
B1
,B B2
B1
B1
3
READ SDR
WRITE SDR
READ DDR
WRITE DDR
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2
B1, B2 B1, B2 B1, B2
INCREMENT ADDRESS B1, B2
INCREMENT ADDRESS B1, B2 B1, B2
INCREMENT ADDRESS
INCREMENT ADDRESS
B1, B2
B1, B2
POWER UP
NO OP
NOTE : 1. State transitions ; B1 =(Load Address), B1=(Increment Address, Continue) B2 =(Read), B2 =(Write) B3 =(Single Data Rate), B3 =(Double Data Rate)
B1, B2
B1, B2 January. 2002 Rev 4.0
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K7D803671B K7D801871B
ABSOLUTE MAXIMUM RATINGS
Parameter Core Supply Voltage Relative to VSS Output Supply Voltage Relative to VSS Voltage on any pin Relative to VSS Output Short-Circuit Current(per I/O) Storage Temperature Symbol VDD VDDQ VIN IOUT TSTR
256Kx36 & 512Kx18 SRAM
Value -0.5 to 3.13 -0.5 to 2.4 -0.5 to VDDQ+0.5 (2.4V MAX) 25 -55 to 125
Unit V V V mA C
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data. Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter Core Power Supply Voltage Output Power Supply Voltage Input High Level Voltage Input Low Level Voltage Input Reference Voltage Clock Input Signal Voltage Clock Input Differential Voltage Clock Input Common Mode Voltage Symbol VDD VDDQ VIH VIL VREF VIN-CLK VDIF-CLK VCM-CLK Min 2.37 1.4 VREF+0.1 -0.3 0.68 -0.3 0.1 0.68 Typ 2.5 1.5 0.75 0.75 Max 2.63 2.0 VDDQ+0.3 VREF-0.1 1.0 VDDQ+0.3 VDDQ+0.6 0.9 Unit V V V V V V V V 1, 4 1, 5 1, 6 1, 2 1, 3 Note
NOTE : 1. These are DC test criteria. DC design criteria is VREF50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width 20% of cycle time). 3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width 20% of cycle time). 4. VIN-CLK specifies the maximum allowable DC level for the differential clock. i.e VIL-CLK and VIH-CLK. 5. VDIF-CLK specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between VIL-CLK and VIH-CLK. 6. VCM-CLK specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock.
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January. 2002 Rev 4.0
K7D803671B K7D801871B
DC CHARACTERISTICS
Parameter Symbol IDD37 IDD35 IDD33 IDD30 IDD25 IDD37 IDD35 IDD33 IDD30 IDD25 ISB1 ILI ILO VOH1 VOL1 VOH2 VOL2
256Kx36 & 512Kx18 SRAM
Min
Max 880 850 750 670 600 830 800 700 620 550 150 1 1 VDDQ VDDQ/2 VDDQ 0.2
Unit
Note
Average Power Supply Operating Current(x36) (Cycle time = tKHKH min)
-
mA
1,2
Average Power Supply Operating Current(x18) (Cycle time = tKHKH min)
-
mA
1,2
Stop Clock Standby Current (VIN=VIH or VIL, K=Low, K=Low) Input Leakage Current (VIN=VSS or VDDQ) Output Leakage Current (VOUT=VSS or VDDQ) Output High Voltage(Programmable Impedance Mode) Output Low Voltage(Programmable Impedance Mode) Output High Voltage(IOH=-0.1mA) Output Low Voltage(IOL=0.1mA)
-1 -1 VDDQ/2 VSS VDDQ-0.2 VSS
mA A A V V V V
1
3 4 5 5
NOTE :1. Minimum cycle. IOUT=0mA. 2. 50% read cycles. 3. |IOH|=(VDDQ/2)/(RQ/5)15% @VOH=VDDQ/2 for 175 RQ 350. 4. |IOL|=(VDDQ/2)/(RQ/5)15% @VOL=VDDQ/2 for 175 RQ 350. 5. Minimum Impedance Mode when ZQ pin is connected to Vss.
PIN CAPACITANCE
Parameter Input Capacitance Data Output Capacitance Symbol CIN COUT Test Condition VIN=0V VOUT=0V Min Max 4 5 Unit pF pF
NOTE : Periodically sampled and not 100% tested.(TA=25C, f=1MHz)
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January. 2002 Rev 4.0
K7D803671B K7D801871B
AC TEST CONDITIONS 1(TA=0 to 70C, VDD=2.37 -2.63V, VDDQ=1.5V)
Parameter Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level Clock Input Timing Reference Level Output Load Symbol VIH/VIL VREF TR/TF
256Kx36 & 512Kx18 SRAM
Value 1.25/0.25 0.75 0.5/0.5 0.75 Cross Point See Below
Unit V V ns V V
Note -
AC TEST OUTPUT LOAD 1
50 50 25 DQ 0.75V 50 50 5pF 0.75V 5pF 0.75V
AC TEST CONDITIONS 2(TA=0 to 70C, VDD=2.37 -2.63V, VDDQ=1.8V)
Parameter Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level Clock Input Timing Reference Level Output Load Symbol VIH/VIL VREF TR/TF Value 1.64/0.18 0.9 0.5/0.5 0.9 Cross Point See Below Unit V V ns V V Note -
AC TEST OUTPUT LOAD 2
50 50 25 DQ 0.9V 50 50 5pF 0.9V 5pF 0.9V
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January. 2002 Rev 4.0
K7D803671B K7D801871B
AC CHARACTERISTICS(For both AC test condition 1 and 2)
Parameter Symbol Min -33 Max Min
256Kx36 & 512Kx18 SRAM
-30 Max Min
-25 Max
Unit
Note
Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width CQ High Pulse Width CQ Low Pulse Width Clock to Echo Clock(CQ) High Clock to Echo Clock(CQ) Low Echo Clock to Output Valid Echo Clock to Output Hold Echo Clock to Output High-Z G Low to Output Low-Z G High to Output High-Z G Low to Output Valid Address Setup Time Address Hold Time Burst Control Setup Time Burst Control Hold Time Data Setup Time Data Hold Time
NOTE : 1. See AC Test Output Load figure 2. Design target is 0ns
tKHKH tKHKL tKLKH tCHCL tCLCH tKXCH tKXCL tCHQV/tCLQV tCHQX/tCLQX tCHQZ/tCLQZ tGLQX tGHQZ tGLQV tAVKH tKHAX tBVKH tKHBX tDVKH tKHDX
3.0 1.3 1.3
tKHKL-0.1 tKLKH-0.1
tKHKL+0.1 tKLKH+0.1
3.3 1.5 1.5
tKHKL-0.2 tKLKH-0.2
tKHKL+0.2 tKLKH+0.2
4.0 1.7 1.7
tKHKL-0.3 tKLKH-0.3
tKHKL+0.3 tKLKH+0.3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1,2 1 1 1 1 1 1
0.5 0.5 -0.2 0.5 0.4 0.4 0.4 0.4 0.4 0.4
1.7 1.7 0.2 0.2 2.1 2.1 -
0.5 0.5 -0.2 0.5 0.4 0.4 0.4 0.4 0.4 0.4
1.9 1.9 0.2 0.2 2.3 2.3 -
0.5 0.5 -0.25 0.5 0.5 0.5 0.5 0.5 0.5 0.5
2.0 2.0 0.25 0.25 2.5 2.5 -
AC CHARACTERISTICS(For AC test condition 1)
Parameter Symbol Min -37 Max Min -35 Max Unit
Note
Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width CQ High Pulse Width CQ Low Pulse Width Clock to Echo Clock(CQ) High Clock to Echo Clock(CQ) Low Echo Clock to Output Valid Echo Clock to Output Hold Echo Clock to Output High-Z G Low to Output Low-Z G High to Output High-Z G Low to Output Valid Address Setup Time Address Hold Time Burst Control Setup Time Burst Control Hold Time Data Setup Time Data Hold Time
NOTE : 1. See AC Test Output Load figure 2. Design target is 0ns
tKHKH tKHKL tKLKH tCHCL tCLCH tKXCH tKXCL tCHQV/tCLQV tCHQX/tCLQX tCHQZ/tCLQZ tGLQX tGHQZ tGLQV tAVKH tKHAX tBVKH tKHBX tDVKH tKHDX
2.7 1.3 1.3
tKHKL-0.1 tKLKH-0.1
tKHKL+0.1 tKLKH+0.1
2.8 1.3 1.3
tKHKL-0.1 tKLKH-0.1
tKHKL+0.1 tKLKH+0.1
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1,2 1 1 1 1 1 1
0.5 0.5 -0.2 0.5 0.4 0.4 0.4 0.4 0.4 0.4
1.7 1.7 0.2 0.2 2.1 2.1 -
0.5 0.5 -0.2 0.5 0.4 0.4 0.4 0.4 0.4 0.4
1.7 1.7 0.2 0.2 2.1 2.1 -
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January. 2002 Rev 4.0
K7D803671B K7D801871B
256Kx36 & 512Kx18 SRAM
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES (Burst Length=4, 2)
READ READ CONTINUE READ CONTINUE READ READ NOP (burst of 4) (burst of 4) (burst of 2)
WRITE NOP 8 WRITE
(burst of 4) CONTINUE READ (burst of 4)
READ
CONTINUE
NOP
1
2
3
4
5
6
7
9
10
11
12
K
tKHKH
K
B1
B2
tBVKH tKHBX
B3
SA
tAVKH
A0 tKHAX
A5
A1
A2
A3
G
tGHQZ tGHQX
tKHDX tDVKH
tGLQV tGLQX
D22 D23 D24 Q31
DQ
QX2
Q01
Q02
Q03
Q04
Q51
Q52
Q53
Q54
Q11
Q12
D21
tKXCH tCHQV tCHQZ tCHLZ
tCHQX
CQ CQ
DON' CARE T UNDEFINED
NOTE 1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc. 2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present. 3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
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January. 2002 Rev 4.0
K7D803671B K7D801871B
256Kx36 & 512Kx18 SRAM
TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES (Burst Length=4, 2, 1)
NOP READ (burst of 4) READ CONTINUE READ READ CONTINUE CONTINUE
WRITE
READ NOP (burst of 1)
READ
NOP 8
(burst of 2)
WRITE 9
CONTINUE READ CONTINUE (burst of 2)
1
2
3
4
5
6
7
10
11
12
K
tKHKH tKHKL tKLKH
K
B1
B2
tBVKH tKHBX
B3
SA
tAVKH
A0 tKHAX
A1
A2 tDVKH
A3
G
tGHQZ tGHQX tKHDX
D21 D22
tGLQV tGLQX
Q31
DQ
QX1
Q01
Q02
Q03
Q04
Q11
tKXCH tCHQV tCHQX tCHQZ tCHLZ
CQ CQ
DON' CARE T UNDEFINED
NOTE : 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc. 2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present. 3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further Continue assertions constitute invalid operations. 4. This device will have an address wraparound if further Continues are applied.
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January. 2002 Rev 4.0
K7D803671B K7D801871B
256Kx36 & 512Kx18 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM. TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 EXTEST IDCODE TDO Output Boundary Scan Register Identification Register
Notes
1 2 1 3 4 3 3 3
SAMPLE-Z Boundary Scan Register BYPASS SAMPLE BYPASS BYPASS BYPASS Bypass Register Boundary Scan Register Bypass Register Bypass Register Bypass Register
SRAM CORE SA SA
1 1 1
TDI
BYPASS Reg. Identification Reg. Instruction Reg. Control Signals
TDO
TMS TCK
NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction dose not places DQs in Hi-Z.
TAP Controller
TAP Controller State Diagram
1 Test Logic Reset
0
0 Run Test Idle 1
Select DR
1
Select IR 0 1 Capture IR 0 Shift IR
1
1
0 1
Capture DR
0
Shift DR
0 1
0
1 1
Exit1 DR
Exit1 IR
0
0
Pause DR
0 0
Pause IR 1 Exit2 IR 1 Update IR 1
0 0
1
Exit2 DR
1 1
Update DR
0
0
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January. 2002 Rev 4.0
K7D803671B K7D801871B
SCAN REGISTER DEFINITION
Part 256Kx36 512Kx18 Instruction Register 3 bits 3 bits Bypass Register 1 bits 1 bits
256Kx36 & 512Kx18 SRAM
ID Register 32 bits 32 bits
Boundary Scan 68 bits 49 bits
ID REGISTER DEFINITION
Part 256Kx36 512Kx18 Revision Number (31:28) 0000 0000 Part Configuration (27:18) 00110 00100 00111 00011 Vendor Definition (17:12) XXXXXX XXXXXX Samsung JEDEC Code (11: 1) 00001001110 00001001110 Start Bit (0) 1 1
BOUNDARY SCAN EXIT ORDER(x36)
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 4A 4C 3A 3B 3C 3D 2B 1B 2D 3F 1D 2F 1F 3H 2H 1H 5A 5B 5K 5L 4L 1K 2K 3K 1M 2M 1P 3M 2P 1T 2T 3T 4R SA SA SA SA SA NC DQ DQ DQ DQ DQ CQ DQ DQ DQ DQ ZQ B1 B2 B3 LBO DQ DQ DQ DQ CQ DQ DQ DQ DQ DQ SA SA SA SA SA SA SA SA DQ DQ DQ DQ DQ CQ DQ DQ DQ DQ G K K NC DQ DQ DQ DQ CQ DQ DQ DQ DQ DQ SA SA SA SA0 SA1 6A 6C 7A 7B 7C 7D 8B 9B 8D 7F 9D 8F 9F 7H 8H 9H 5C 5G 5H 6L 9K 8K 7K 9M 8M 9P 7M 8P 9T 8T 7P 7T 6R 5T 5R 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOUNDARY SCAN EXIT ORDER(x18)
26 27 28 29 30 31 32 4A 4C 3A 3B 3C 3D 2B SA SA SA SA SA NC DQ DQ DQ DQ 33 34 35 36 37 38 39 40 41 42 43 1D 2F 3H 1H 5A 5B 5K 5L 4L 2K 1M DQ CQ DQ DQ DQ DQ ZQ B1 B2 B3 LBO DQ DQ G K K NC DQ DQ CQ DQ 44 45 46 47 48 49 3M 2P 1T 3P 3T 4R DQ DQ DQ SA SA SA DQ SA SA SA SA0 SA1 8T 7P 7T 6R 5T 5R 6 5 4 3 2 1 5C 5G 5H 6L 9K 7K 8M 9P 14 13 12 11 10 9 8 7 8H 15 9F 16 9B 8D 7F 19 18 17 SA SA SA SA SA SA 6A 6C 7A 7B 7C 7D 25 24 23 22 21 20
1.Pin 6L is reserved for Mode Pin and the scanned data is fixed to "0" 2.Pin 3D is reserved for Address bit for 16Mb density and the scanned data is fixed to "0"
1.Pin 6L is reserved for Mode Pin and the scanned data is fixed to "0" 2.Pin 3D is reserved for Address bit for 16Mb density and the scanned data is fixed to "0"
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January. 2002 Rev 4.0
K7D803671B K7D801871B
JTAG DC OPERATING CONDITIONS
Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(IOH=-2mA) Output Low Voltage(IOL=2mA) Symbol VDD VIH VIL VOH VOL Min 2.37 1.7 -0.3 2.1 VSS
256Kx36 & 512Kx18 SRAM
Typ 2.5 -
Max 2.63 VDD+0.3 0.7 VDD 0.2
Unit V V V V V
Note
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 5.
Symbol VIH/VIL TR/TF
Min 2.5/0.0 1.0/1.0 1.25
Unit V ns V
Note
1
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tCLQV Min 50 20 20 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns Note
JTAG TIMING DIAGRAM
TCK
tCHCH tCHCL tMVCH tCHMX tCLCH
TMS
tDVCH
tCHDX
TDI
tCLQV
TDO
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January. 2002 Rev 4.0
K7D803671B K7D801871B
153 BGA PACKAGE DIMENSIONS
256Kx36 & 512Kx18 SRAM
0.60 0.10 0.024 0.004 U T RPNML K J HGF EDCBA
1.27 0.050 987654321
20.50 0.10 0.807 0.004
22.00 0.10 0.866 0.004
12.50 0.10 0.492 0.004 14.00 0.10 0.551 0.004
0.56 0.04 0.022 0.002 0.90 0.10 0.035 0.004 2.21 MAX 0.087 0.15 0.006 MAX
0.3/0.012MAX
153-
TOP VIEW
BOTTOM VIEW
NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball to PCS Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX.
153 BGA PACKAGE THERMAL CHARACTERISTICS
Parameter Junction to Ambient(at still air) Junction to Case Junction to Board Symbol Theta_JA Theta_JC Theta_JB Thermal Resistance 30.0 5.9 4.8 Unit C/W C/W C/W 2W Heating Note 1W Heating
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA.
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1.27 0.050 0.75 0.15 0.030 0.006
January. 2002 Rev 4.0

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